The invention relates to passivation or dielectric layers used in, for example, circuit structures.
Dielectric layers or films are used to electrically isolate one device from another in a circuit structure and one level of conductor from another in multi-level interconnect systems such as found in many integrated circuit structures. A microprocessor, for example, may have five or more levels of interconnect over a substrate such as a semiconductor substrate.
There can be a significant difference between various dielectric layers or films in a multi-level interconnect system or structure. For example, pre-metal dielectric (PMD) layers or films are typically used between the substrate or device base (e.g., the substrate containing active devices therein/thereon), or other local-interconnect level material, and the first interconnect level (e.g., Metal 1). PMD layers or films can typically be deposited (and densified if necessary) at a higher temperature than is possible for intermetal dielectric layers. Furthermore, PMD films can be flowed and reflowed at temperatures in excess of 700xc2x0 C. to promote gap fill. As interconnect structures are introduced over a substrate, the maximum temperature for introduction of a dielectric layer or film tends to be reduced, because metal interconnects tend to melt at temperatures in excess of 400xc2x0 C. (e.g., at aluminum or copper melting temperatures).
The PMD layer or film isolates devices in an integrated circuit structure in two ways. It isolates devices electrically from interconnect layers, and it isolates devices physically from contamination sources such as mobile ions (e.g., from post-processing and handling). Mobile ions such as sodium and potassium tend to degrade essential device characteristics such as the threshold voltage of a transistor device.
As device densities increase on a circuit structure or substrate, the ability of the PMD layer or film to achieve void-free gap fill becomes increasingly important. For example, in sub 0.25 micron (um) devices, one criteria for filling a gap in a PMD process is 0.1 microns (xcexcm) with a 5 to 1 aspect ratio.
Borophosphosilicate glass (BPSG)-silicon dioxide (SiO2) is one well known material for a PMD layer or film. BPSG typically contains about two to six weight percent each of boron and phosphorous. BPSG is typically deposited using thermal chemical vapor deposition (CVD) at 400 to 700xc2x0 C., and then annealed (reflowed) at 700 to 1000xc2x0 C. In general, the phosphorus in BPSG acts as a gettering agent for any mobile ions that may diffuse toward the devices (e.g., transistors), while the boron provides good gap fill because it tends to soften the layer after the reflow anneal.
In a typical fabrication process of a state of the art integrated circuit structure, a thin layer of silicon nitride (Si3N4) is introduced over the substrate as an initial dielectric layer or film followed by, for example, a BPSG layer or film. In addition to its passivation property, the silicon nitride also serves in one instance as an etch stop in planarizing a subsequently introduced PMD layer or film, such as a BPSG layer or film.
As noted above, gap fill of a PMD layer or film is increasingly important as device densities increase. The gap fill properties of a BPSG layer or film is optimized by annealing at more than 800xc2x0 C. The high temperature anneal tends to increase the reflow ability of the BPSG. However, one drawback to the high temperature anneal and reflow process is that the BPSG material tends to consume nitrogen from the underlying silicon nitride layer or film. The nitride consumption tends to degrade the insulating properties of the silicon nitride material. Thus, what is needed is a way to control the nitrogen consumption of nitrogen-containing layers or films in conjunction with a thermal processing in the presence of phosphorous.
In one embodiment, a method includes, over a circuit substrate, forming an aggregate comprising a barrier layer between a first dielectric layer comprising nitrogen and a second dielectric layer comprising phosphorus. In this embodiment, the method also includes, after forming the aggregate, thermally treating the circuit substrate. A suitable introduction point for implementing the method described herein is in a PMD layer or film, wherein the circuit substrate comprises a device base and at least one metal layer and the aggregate is introduced between the device base and the at least one metal layer. Suitable barrier layers include dielectric materials, particularly silicates such as borosilicate glass (BSG) or undoped silicate glass (USG). A thin film of, for example, BSG or USG between a silicon nitride film an d BPSG material tends to reduce the consumption during reflow (thermally annealing) the BPSG.
In another embodiment, the invention relates to an apparatus. The apparatus includes, in one aspect, a circuit substrate and an aggregate comprising a barrier layer between a first dielectric layer comprising nitrogen and a second dielectric layer comprising phosphorus. One example is an aggregate as a PMD layer or film comprising a barrier layer of a dielectric material such as BSG or USG disposed between a silicon nitride layer and a BPSG layer as the aggregate of a PMD film.
Additional features, embodiments, and benefits will be evident in view of the figures and detailed description presented herein.